can microprogram FSM based design be pipelined

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JensenBreck
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Εγγραφή: Παρ Σεπ 22, 2017 12:48 am

can microprogram FSM based design be pipelined

Μη αναγνωσμένη δημοσίευσηαπό JensenBreck » Παρ Σεπ 22, 2017 3:15 pm

Hello,

I am designing an FSM based processor which works fine but now I want to pipeline it to achieve more instruction throughput. How can I do it??

I have a confusion that in normal FSM based design there is one state of the machine during each clock cycle of instruction execution but when pipelining that design means there are multiple instructions in execution during each clock cycle that means there will not be a single state i.e. some instruction will be in fetch state while the other is in decoding state and so on. So I want to know that whether I have to remove FSM from my design for pipelining or is there any other option with FSM for pipelining??


Thanks in advance





I didn't find the right solution from the internet.
References:
https://forums.xilinx.com/t5/General-Te ... d-p/205713

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VincentGR
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Re: can microprogram FSM based design be pipelined

Μη αναγνωσμένη δημοσίευσηαπό VincentGR » Παρ Σεπ 22, 2017 6:18 pm

Sorry can't help you, never tried to do something like this.
Εικόνα FAN
http://partsfromthepast.blogspot.gr/
To blit, or not to blit?


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